Conference and Journal Publications

2018

  • Hardware-Software Co-Optimization of Garbage Collection for Efficient Memory Management in Dynamic Languages
    Mohamed Ismail and G. Edward Suh
    To appears in the Proceedings of the 2018 International Symposium on Memory Management (ISMM), June 2018.
  • Reverse Engineering Convolutional Neural Networks Through Side-channel Information Leaks
    Weizhe Hua, Zhiru Zhang, and G. Edward Suh
    To appear in the Proceedings of the 55th Design Automation Conference (DAC), June 2018.
  • FPGA-Based Remote Power Side-Channel Attacks
    Mark Zhao and G. Edward Suh
    T
    o appear in the Proceedings of the IEEE Symposium on Security and Privacy, May 2018.
  • TWiCe: Time Window Counter Based Row Refresh to Prevent Row-hammering
    Eojin Lee, Sukhan Lee, G. Edward Suh, and Jung Ho Ahn
    To appears in IEEE Computer Architecture Letters, 2018.

2017

  • Komodo: Using Verification to Disentangle Secure-Enclave Hardware from Software
    Andrew Ferraiuolo, Andrew Baumann, Chris Hawblitzel, Bryan Parno
    Proceedings of the 26th ACM Symposium on Operating Systems Principles (SOSP), October 2017.
  • Secure Information Flow Verification with Mutable Dependent Types
    Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh
    Proceedings of the 54th Design Automation Conference (DAC), June 2017.
    PDF ]
  • Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
    Andrew Ferraiuolo, Rui Xu, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh
    Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2017.
    PDF ]
  • Secure Dynamic Memory Scheduling Against Timing Channel Attacks
    Yao Wang, Benjamin Wu, and G. Edward Suh
    Proceedings of the 23rd International Symposium on High-Performance Computer Architecture (HPCA), February 2017.
    PDF ]

2016

  • Efficient Data Supply for Hardware Accelerators with Prefetching and Access/Execute Decoupling
    Tao Chen and G. Edward Suh
    Proceedings of the 49th Annual International Symposium on Microarchitecture (MICRO), October 2016.
  • Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation
    Taejoon Song, Daniel Lo, and G. Edward Suh
    Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), August 2016.
  • SecDCP: Secure Dynamic Cache Partitioning for Efficient Timing Channel Protection
    Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh
    Proceedings of the 53rd Design Automation Conference (DAC), June 2016.
  • Lattice Priority Scheduling: Low-Overhead Timing Channel Protection for a Shared Memory Controller
    Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh
    Proceedings of the 22nd International Symposium on High-Performance Computer Architecture (HPCA), February 2016.
    PDF ]

2015

  • Execution Time Prediction for Energy-Efficient Hardware Accelerators
    Tao Chen, Alex Rucker, and G. Edward Suh
    Proceedings of the 48th Annual International Symposium on Microarchitecture (MICRO), December 2015.
    [ PDF ]
  • Prediction-Guided Performance-Energy Trade-off for Interactive Applications
    Daniel Lo, Taejoon Song, and G. Edward Suh
    Proceedings of the 48th Annual International Symposium on Microarchitecture (MICRO), December 2015.
    [ PDF ]
  • Improving Worst-Case Cache Performance through Selective Bypassing and Register-Indexed Cache
    Mohamed Ismail, Daniel Lo, and G. Edward Suh
    Proceedings of the the 52nd Design Automation Conference (DAC), June 2015.
    [ PDF ]
  • A Hardware Design Language for Timing-Sensitive Information-Flow Security
    Danfeng Zhang, Yao Wang, G. Edward Suh, and Andrew C. Myers
    Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015.
    [ ACM-Authorize ]
  • Run-Time Monitoring with Adjustable Overheads Using Dataflow-Guided Filtering
    Daniel Lo, Tao Chen, Mohamed Ismail, and G. Edward Suh
    Proceedings of the 21st International Symposium on High Performance Computer Architecture (HPCA), February 2015.
    [ PDF ]

2014

  • Author Retrospective: Analytical Cache Models With Applications to Cache Partitioning
    G. E. Suh, G. Kurian, S. Devadas, and L. Rudolph
    International Conference on Supercomputing 25th Anniversary Volume, 2014.
    [ ACM-Authorize ]
  • Author Retrospective: AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing
    G. E. Suh, C. Fletcher, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas
    International Conference on Supercomputing 25th Anniversary Volume, 2014.
    [ ACM-Authorize ]
  • Understanding Sources of Variations in Flash Memory for Physical Unclonable Functions
    Sarah Q. Xu, Wing-kei Yu, G. Edward Suh, and Edwin C. Kan
    Proceedings of the 2014 International Memory Workshop (IMW), May 2014.
    [ PDF ]
  • Slack-Aware Opportunistic Monitoring for Real-Time Systems
    Daniel Lo, Mohamed Ismail, Tao Chen, and G. Edward Suh
    Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), April 2014.
    [ PDF ]
  • Timing Channel Protection for Memory Controllers
    Yao Wang, Andrew Ferraiuolo, and G. Edward Suh
    Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014.
    [ PDF ]
  • Low-Overhead and High Coverage Run-Time Race Detection Through Selective Meta-data Management
    Ruirui Huang, Erik Halberg, Andrew Ferraiuolo, and G. Edward Suh
    Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014.
    [ PDF ]

2013

  • Non-Race Concurrency Bug Detection Through Order-Sensitive Critical Sections
    Ruirui Huang, Erik Halberg, and G. Edward Suh
    Proceedings of the 40th International Symposium on Computer Architecture (ISCA), June 2013.
    [ ACM-Authorize ]
  • Hiding Information in Flash Memory
    Yinglei Wang, Wing-kei Yu, Sarah Q. Xu, Edwin Kan, and G. Edward Suh
    Proceedings of the IEEE Symposium on Security and Privacy, May 2013.
    [ PDF ]
  • Quardrisection-Based Task Mapping on Many-Core Processors for Energy-Efficient On-Chip Communication
    Nithin Michael, Yao Wang, Kevin Tang and G. Edward Suh
    Proceedings of the 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013.
    [ PDF ]
  • Optimal and Heuristic Application-Aware Oblivious Routing
    Michel Kinsy, Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, G. Edward Suh, and Srinivas Devadas
    IEEE Transactions on Computers, vol.62, no.1, pp.59–73, January 2013.
    [ IEEE ]

2012

  • Fast Development of Hardware-Based Run-Time Monitors Through Architecture Framework and High-Level Synthesis
    Mohamed Ismail and G. Edward Suh
    Proceedings of the 30th International Conference on Computer Design (ICCD), October 2012.
    [ PDF ]
  • High-Performance Parallel Accelerator for Flexible and Efficient Instruction-Grained Run-Time Monitoring
    Daniel Y. Deng and G. Edward Suh
    Proceedings of the 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), June 2012.
    [ PDF ]
  • Worst-Case Execution Time Analysis for Parallel Run-Time Monitoring
    Daniel Lo and G. Edward Suh
    Proceedings of the 49th Design Automation Conference (DAC), June 2012.
    [ ACM-Authorize ]
  • Efficient Timing Channel Protection for On-Chip Networks
    Yao Wang and G. Edward Suh
    Proceedings of the 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2012.
    [ PDF ]
  • Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints
    Yinglei Wang, Wing-kei Yu, Shuo Wu, Greg Malysa, G. Edward Suh, and Edwin Kan
    Proceedings of the IEEE Symposium on Security and Privacy, May 2012.
    [ PDF ]
  • On the Performance of Averaged Optimal Routing
    Nithin Michael, Ao Tang, and G. Edward Suh
    Proceedings of the 46th Annual Conference on Information Sciences and Systems (CISS), March 2012.
    [ PDF ]

2011

  • Precise Exception Support for Decoupled Run-Time Monitoring Architectures
    Daniel Y. Deng and G. Edward Suh
    Proceedings of the 29th International Conference on Computer Design (ICCD), September 2011.
    [ IEEE ]
  • FlexCache: Field Extensible Cache Controller Architecture Using On-Chip Reconfigurable Fabric
    Daniel Lo, Greg Malysa and G. Edward Suh
    Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL), September 2011.
    [ IEEE ]
  • A Non-Volatile Microcontroller with Integrated Floating-Gate Transistors
    Wing-kei Yu, Shantanu Rajwade, Sung-En Wang, Bob Lian, G. Edward Suh, Edwin Kan
    Proceedings of the 5th Workshop on Dependable and Secure Nanocomputing (WDSN), June 2011.
    [ IEEE ]
  • Systematic Security Assessment at an Early Processor Design Stage
    Ruirui Huang, David Grawrock, David C. Doughty, G. Edward Suh
    Proceedings of the 4th International Conference on Trust and Trustworthy Computing (TRUST), June 2011.
    [ LNCS ]
  • Extracting Device Fingerprints from Flash Memory Exploiting Physical Variations
    Pravin Prabhu, Ameen Akel, Laura, Wing-Kei S. Yu, G. Edward Suh, Edwin Kan, Steven Swanson
    Proceedings of the 4th International Conference on Trust and Trustworthy Computing (TRUST), June 2011.
    [ LNCS ]
  • SRAM-DRAM Hybrid Memory with Applications to Efficient Register Files in Fine-Grained Multi-Threading
    Wing-kei Yu, Ruirui Huang, Sarah Xu, Sung-En Wang, Edwin Kan, and G. Edward Suh
    Proceedings of the 38th International Symposium on Computer Architecture (ISCA), June 2011.
    [ ACM-Authorize ]
  • Analysis of Application-Aware On-Chip Routing under Traffic Uncertainty
    Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh, and Christopher Batten
    Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2011.
    [ PDF ]

2010

  • Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
    Daniel Y Deng, Daniel Lo, Greg Malysa, Skyler Schneider, and G. Edward Suh
    Proceedings of the 43rd Annual International Symposium on Microarchitecture (MICRO), December 2010.
    [ IEEE ]
  • Low Power Nonvolatile SRAM Circuit with Integrated Low Voltage Nanocrystal PMOS Flash
    Shantanu Rajwade, Wing-kei Yu, Sarah Xu, Tuo-Hung Hou, G. Edward Suh, and Edwin Kan
    Proceedings of the 23rd IEEE International System-On-Chip Conference, September 2010.
    [ PDF ]
  • IVEC: Off-Chip Memory Integrity Protection for Both Security and Reliability
    Ruirui Huang, and G. Edward Suh
    Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), June 2010.
    [ ACM ]
  • Orthrus: Efficient Software Integrity Protection on Multi-Cores
    Ruirui Huang, Daniel Y. Deng, and G. Edward Suh
    Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), March 2010.
    [ ACM ]

2009

  • Hardware Authentication Leveraging Performance Limits in Detailed Simulations and Emulations
    Daniel Y. Deng, Andrew H. Chan, and G. Edward Suh
    Proceedings of the 46th Design Automation Conference (DAC’09), July 2009.
    [ ACM ]
  • Static Virtual Channel Allocation in Oblivious Routing
    Keun Sup Shim, Myong Hyon Cho, Michel Kinsy, Tina Wen, G. Edward Suh, and Srinivas Devadas
    Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2009.
    [ ACM ]
  • Application-Aware Deadlock-Free Oblivious Routing
    Michel Kinsy, Myong Hyon Cho, Tina Wen, Edward Suh, Marten van Dijk, and Srinivas Devadas
    Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA), June 2009. [ ACM ]

2008

  • Diastolic Arrays: Throughput-Driven Reconfigurable Computing
    Myong Hyon Cho, Chih-Chi Cheng, Michel Kinsy, G. Edward Suh, and Srinivas Devadas
    Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’08), November 10-23, 2008.
    [ IEEE ]
  • Design and Implementation of PUF-Based “Unclonable” RFID ICs for Anti-Counterfeiting and Security Applications
    Srinivas Devadas, G. Edward Suh, Sid Paral, Richard Sowell, Thomas Ziola, and Vivek Khandelwal
    Proceedings of the IEEE International Conference on RFID, April 16-17, 2008.
    [ IEEE ]

2007

  • AEGIS: A Single-Chip Secure Processor
    G. Edward Suh, Charles W. O’Donnell, and Srinivas Devadas
    IEEE Design & Test of Computers, vol.24, no.6, pp.570-580, Nov.-Dec. 2007.
    [ IEEE ]
  • Memoization Attacks and Copy Protection in Partitioned Applications
    Charles W. O’Donnell, G. Edward Suh, Marten van Dijk, and Srinivas Devadas
    Proceedings of the 2007 IEEE Workshop on Information Assurance, West Point, NY, June 2007.
    [ PDF ]
  • Physical Unclonable Functions for Device Authentication and Secret Key Generation
    G. Edward Suh, and Srinivas Devadas
    Proceedings of the 44th Design Automation Conference (DAC’07), San Diego, CA, June 2007.
    [ PDF ]

2006

  • Speeding up Exponentiation using an Untrusted Computational Resource
    Marten van Dijk, Dwaine Clarke, Blaise Gassend, G. Edward Suh, and Srinivas Devadas
    Designs, Codes and Cryptography, Volume 39, Number 2, Pages 253-273, May 2006.
    [ PDF ]

2005

  • Extracting Secret Keys from Integrated Circuits
    Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, and Srinivas Devadas
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 10, Pages 1200-1205, October 2005.
    [ PDF ]
  • Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
    G. Edward Suh, Charles W. O’Donnell, Ishan Sachdev, and Srinivas Devadas
    Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005. (This memo is a slightly updated version)
    [ PS ] [ PDF ] [ SLIDES(PPT) ]
  • Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data
    Dwaine Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk and Srinivas Devadas
    Proceedings of the 2005 IEEE Symposium on Security and Privacy (This memo is a slightly updated version), 2005.
    [ PS ] [ PDF ]

2004

  • Secure Program Execution via Dynamic Information Flow Tracking
    G. Edward Suh, Jae W. Lee, David X. Zhang, and Srinivas Devadas
    Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI), pages 85-96, Boston, MA, October 2004.
    [ PS ] [ PDF ] [ SLIDES ]
  • A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication Applications
    Jae W. Lee, Daihyun Lim, Blaise Gassend, G. Edward Suh, Marten van Dijk, and Srinivas Devadas
    Proceedings of the Symposium on VLSI Circuits, pages 176-179, Honolulu, HI, June 2004.
    [ PS ] [ PDF ]
  • Dynamic Partitioning of Shared Cache Memory
    G. Edward Suh, Larry Rudolph, and Srinivas Devadas
    The Journal of Supercomputing, 28(1), pages 7-26, April 2004.
    [ PDF ]

2003

  • Efficient Memory Integrity Verification and Encryption for Secure Processors
    G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, and Srinivas Devadas
    Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO36), pages 339-350, San Diego, CA, December 2003.
    [ PS ] [ PDF ] [ SLIDES ]
  • Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking
    Dwaine Clarke, Srinivas Devadas, Marten van Dijk, Blaise Gassend, and G. Edward Suh
    Proceedings of the 9th International Conference on the Theory and Application of Cryptology and Information Security (Asiacrypt 2003), Lecture Notes in Computer Science (LNCS), Vol. 2894, pages 188-207, Taipei, Taiwan, November 2003.
    [ PS ] [ PDF ]
  • The AEGIS Processor Architecture for Tamper-Evident and Tamper-Resistant Processing
    G. Edward Suh, Blaise Gassend, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas
    Proceedings of the 17th International Conference on Supercomputing (ICS’03), pages 160-171, San Francisco, CA, June 2003. (Revised version)
    [ PS ] [ PDF ] [ SLIDES ]
  • Intelligent SRAM (ISRAM) for Improved Embedded System Performance
    Prabhat Jain, G. Edward Suh, and Srinivas Devadas
    Proceedings of the 40th Design Automation Conference (DAC’03), pages 869-874, Anaheim, CA, June 2003.
    [ PS ] [ PDF ]
  • Caches and Hash Trees for Efficient Memory Integrity Verification
    Blaise Gassend, G. Edward Suh, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas
    Proceedings of the High Performance Computer Architecture 9 (HPCA9), pages 295-306, Anaheim, CA, February 2003.
    [ PS ] [ PDF ]

2002

  • A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
    G. Edward Suh, Srinivas Devadas, and Larry Rudolph
    Proceedings of the High Performance Computer Architecture 8 (HPCA8), pages 117-118, Boston, MA, February 2002.
    [ PS ] [ PDF ] [ SLIDES ]

2001

  • Effects of Memory Performance on Parallel Job Scheduling
    G. Edward Suh, Larry Rudolph, and Srinivas Devadas
    Proceedings of the 7th International Workshop on Job Scheduling Strategies for for Parallel Processing (JSSPP 2001), Lecture Notes in Computer Science (LNCS), Vol. 2221, pages 116-132, Cambridge, MA, June 2001.
    [ PS ] [ PDF ]
  • Dynamic Cache Partitioning for Simultaneous Multithreading Systems
    G. Edward Suh, Larry Rudolph, and Srinivas Devadas
    Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS’01), pages 635-641, Anaheim, CA, August 2001. (Best paper award)
    [ PS ] [ PDF ] [ SLIDES ]
  • Analytical Cache Models with Application to Cache Partitioning
    G. Edward Suh, Srinivas Devadas, and Larry Rudolph
    Proceedings of the 15th International Conference on Supercomputing (ICS’01), pages 1-12, Sorrento, Italy, June 2001.
    [ PS ] [ PDF ] [ SLIDES ]

Book Chapters

  • A. Sadeghi, D. Naccache (Eds.), Towards Hardware-Intrinsic Security, Springer, 2010. (ISBN: 978-3-642-14451-6)

M.S. Theses/Ph.D. Dissertations

  • Efficient and Verifiable Timing Channel Protection for Multi-Core Processors
    Yao Wang
    Doctoral Dissertation, Cornell University, January 2017.
    [ PDF ]
  • Prediction-Guided Performance-Energy Trade-off with Continuous Run-time Adaptation
    Taejoon Song
    M.S. Thesis, Cornell University, May 2016.
    [ PDF ]
  • Flexible and Efficient Accelerator Architecture for Runtime Monitoring
    Danny Y. Deng
    Doctoral Dissertation, Cornell University, May 2016.
    [ PDF ]
  • Hybrid Memories for Energy Efficient Computing Systems
    Wing-Kei (KK) Yu
    Doctoral Dissertation, Cornell University, January 2016.
  • Information Flow Analysis for Security Verification of Hardware
    Rui Xu
    M.S. Thesis, Cornell University, August 2015.
  • Hardware Architectures For Secure, Reliable, And Energy-Efficient Real-Time Systems
    Daniel Lo
    Doctoral Dissertation, Cornell University, August 2015.
    [ eCommons ]
  • Detecting and Mitigating Concurrency Bugs
    Ruirui (Ray) Huang
    Doctoral Dissertation, Cornell University, May 2013.
    [ eCommons ]
  • AEGIS: A Single-Chip Secure Processor
    G. Edward Suh
    MIT CSAIL CSG-TR-489 (Doctoral Dissertation), September 2005.
    [ PDF ]

Unrefereed Publications

ACM and IEEE-mandated Copyright Notice

The documents listed above are posted as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author’s copyright. These works may not be reposted without the explicit permission of the copyright holder.