As the traditional technology scaling slows down, future computing will need to rely increasingly on architecture and software-level customization for more efficiency. In this context, there are two main ways to improve efficiency: build heterogeneous hardware that better match workload characteristics and remove inefficiencies in abstraction layers by optimizing multiple layers together. In this project, we are developing automated tools along with new architecture designs to allow a system to be quickly customized for given applications and environments.
As the first example, we investigated how exposing application-level response-time requirements to lower-level layers and co-optimizing them can reduce the overall energy consumption. In particular, we developed new prediction-guided DVFS frameworks for processing cores as well as accelerators. The frameworks enable developing application-specific DVFS controller with minimal human efforts, and lead to significant energy savings over today’s Linux power governors.
Tao Chen, Alex Rucker, and G. Edward Suh, Execution Time Prediction for Energy-Efficient Hardware Accelerators, Proceedings of the 48th Annual International Symposium on Microarchitecture (MICRO), December 2015.
Daniel Lo, Taejoon Song, and G. Edward Suh, Prediction-Guided Performance-Energy Trade-off for Interactive Applications, Proceedings of the 48th Annual International Symposium on Microarchitecture (MICRO), December 2015.