Suh Research Group

Publications

Conference and Journal Publications

2017

  • Andrew Ferraiuolo, Rui Xu, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh, Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis, To appear in Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2017. [ PDF ]
  • Yao Wang, Benjamin Wu, and G. Edward Suh, Secure Dynamic Memory Scheduling Against Timing Channel Attacks, To appear in Proceedings of the 23rd International Symposium on High-Performance Computer Architecture (HPCA), February 2017. [ PDF ]

2016

  • Tao Chen and G. Edward Suh, Efficient Data Supply for Hardware Accelerators with Prefetching and Access/Execute Decoupling, Proceedings of the 49th Annual International Symposium on Microarchitecture (MICRO), October 2016.
  • Taejoon Song, Daniel Lo, and G. Edward Suh, Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), August 2016.
  • Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh, SecDCP: Secure Dynamic Cache Partitioning for Efficient Timing Channel Protection, Proceedings of the the 53rd Design Automation Conference (DAC), June 2016.
  • Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh, Lattice Priority Scheduling: Low-Overhead Timing Channel Protection for a Shared Memory Controller, Proceedings of the 22nd International Symposium on High-Performance Computer Architecture (HPCA), February 2016. [ PDF ]

2015

  • Tao Chen, Alex Rucker, and G. Edward Suh, Execution Time Prediction for Energy-Efficient Hardware Accelerators, Proceedings of the 48th Annual International Symposium on Microarchitecture (MICRO), December 2015. [ PDF ]
  • Daniel Lo, Taejoon Song, and G. Edward Suh, Prediction-Guided Performance-Energy Trade-off for Interactive Applications, Proceedings of the 48th Annual International Symposium on Microarchitecture (MICRO), December 2015. [ PDF ]
  • Mohamed Ismail, Daniel Lo, and G. Edward Suh, Improving Worst-Case Cache Performance through Selective Bypassing and Register-Indexed Cache, Proceedings of the the 52nd Design Automation Conference (DAC), June 2015. [ PDF ]
  • Danfeng Zhang, Yao Wang, G. Edward Suh, and Andrew C. Myers, A Hardware Design Language for Timing-Sensitive Information-Flow Security, Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015. [ ACM-Authorize ]
  • Daniel Lo, Tao Chen, Mohamed Ismail, and G. Edward Suh, Run-Time Monitoring with Adjustable Overheads Using Dataflow-Guided Filtering, Proceedings of the 21st International Symposium on High Performance Computer Architecture (HPCA), February 2015. [ PDF ]

2014

  • G. E. Suh, G. Kurian, S. Devadas, and L. Rudolph, “Author Retrospective: Analytical Cache Models With Applications to Cache Partitioning”, International Conference on Supercomputing 25th Anniversary Volume, 2014. [ ACM-Authorize ]
  • G. E. Suh, C. Fletcher, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, “Author Retrospective: AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing”, International Conference on Supercomputing 25th Anniversary Volume, 2014. [ ACM-Authorize ]
  • Sarah Q. Xu, Wing-kei Yu, G. Edward Suh, and Edwin C. Kan, Understanding Sources of Variations in Flash Memory for Physical Unclonable Functions, Proceedings of the 2014 International Memory Workshop (IMW), May 2014. [ PDF ]
  • Daniel Lo, Mohamed Ismail, Tao Chen, and G. Edward Suh, Slack-Aware Opportunistic Monitoring for Real-Time Systems, Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), April 2014. [ PDF ]
  • Yao Wang, Andrew Ferraiuolo, and G. Edward Suh, Timing Channel Protection for Memory Controllers, Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014. [ PDF ]
  • Ruirui Huang, Erik Halberg, Andrew Ferraiuolo, and G. Edward Suh, Low-Overhead and High Coverage Run-Time Race Detection Through Selective Meta-data Management, Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014. [ PDF ]

2013

  • Ruirui Huang, Erik Halberg, and G. Edward Suh, Non-Race Concurrency Bug Detection Through Order-Sensitive Critical Sections, Proceedings of the 40th International Symposium on Computer Architecture (ISCA), June 2013. [ ACM-Authorize ]
  • Yinglei Wang, Wing-kei Yu, Sarah Q. Xu, Edwin Kan, and G. Edward Suh, Hiding Information in Flash Memory, Proceedings of the IEEE Symposium on Security and Privacy, May 2013. [ PDF ]
  • Nithin Michael, Yao Wang, Kevin Tang and G. Edward Suh, Quardrisection-Based Task Mapping on Many-Core Processors for Energy-Efficient On-Chip Communication, Proceedings of the 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. [ PDF ]
  • Michel Kinsy, Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, G. Edward Suh, and Srinivas Devadas, Optimal and Heuristic Application-Aware Oblivious Routing, IEEE Transactions on Computers, vol.62, no.1, pp.59–73, January 2013. [ IEEE ]

2012

  • Mohamed Ismail and G. Edward Suh, Fast Development of Hardware-Based Run-Time Monitors Through Architecture Framework and High-Level Synthesis, Proceedings of the 30th International Conference on Computer Design (ICCD), October 2012. [ PDF ]
  • Daniel Y. Deng and G. Edward Suh, High-Performance Parallel Accelerator for Flexible and Efficient Instruction-Grained Run-Time Monitoring, Proceedings of the 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), June 2012. [ PDF ]
  • Daniel Lo and G. Edward Suh, Worst-Case Execution Time Analysis for Parallel Run-Time Monitoring, Proceedings of the 49th Design Automation Conference (DAC), June 2012. [ ACM-Authorize ]
  • Yao Wang and G. Edward Suh, Efficient Timing Channel Protection for On-Chip Networks, Proceedings of the 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2012. [ PDF ]
  • Yinglei Wang, Wing-kei Yu, Shuo Wu, Greg Malysa, G. Edward Suh, and Edwin Kan, Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints, Proceedings of the IEEE Symposium on Security and Privacy, May 2012. [ PDF ]
  • Nithin Michael, Ao Tang, and G. Edward Suh, On the Performance of Averaged Optimal Routing, Proceedings of the 46th Annual Conference on Information Sciences and Systems (CISS), March 2012. [ PDF ]

2011

  • Daniel Y. Deng and G. Edward Suh, Precise Exception Support for Decoupled Run-Time Monitoring Architectures, Proceedings of the 29th International Conference on Computer Design (ICCD), September 2011. [ IEEE ]
  • Daniel Lo, Greg Malysa and G. Edward Suh, FlexCache: Field Extensible Cache Controller Architecture Using On-Chip Reconfigurable Fabric, Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL), September 2011. [ IEEE ]
  • Wing-kei Yu, Shantanu Rajwade, Sung-En Wang, Bob Lian, G. Edward Suh, Edwin Kan, A Non-Volatile Microcontroller with Integrated Floating-Gate Transistors, Proceedings of the 5th Workshop on Dependable and Secure Nanocomputing (WDSN), June 2011. [ IEEE ]
  • Ruirui Huang, David Grawrock, David C. Doughty, G. Edward Suh, Systematic Security Assessment at an Early Processor Design Stage, Proceedings of the 4th International Conference on Trust and Trustworthy Computing (TRUST), June 2011. [ LNCS ]
  • Pravin Prabhu, Ameen Akel, Laura, Wing-Kei S. Yu, G. Edward Suh, Edwin Kan, Steven Swanson, Extracting Device Fingerprints from Flash Memory Exploiting Physical Variations, Proceedings of the 4th International Conference on Trust and Trustworthy Computing (TRUST), June 2011. [ LNCS ]
  • Wing-kei Yu, Ruirui Huang, Sarah Xu, Sung-En Wang, Edwin Kan, and G. Edward Suh, SRAM-DRAM Hybrid Memory with Applications to Efficient Register Files in Fine-Grained Multi-Threading, Proceedings of the 38th International Symposium on Computer Architecture (ISCA), June 2011. [ ACM-Authorize ]
  • Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh, and Christopher Batten, Analysis of Application-Aware On-Chip Routing under Traffic Uncertainty, Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2011. [ PDF ]

2010

  • Daniel Y Deng, Daniel Lo, Greg Malysa, Skyler Schneider, and G. Edward Suh, Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric, Proceedings of the 43rd Annual International Symposium on Microarchitecture (MICRO), December 2010. [ IEEE ]
  • Shantanu Rajwade, Wing-kei Yu, Sarah Xu, Tuo-Hung Hou, G. Edward Suh, and Edwin Kan, Low Power Nonvolatile SRAM Circuit with Integrated Low Voltage Nanocrystal PMOS Flash, Proceedings of the 23rd IEEE International System-On-Chip Conference, September 2010. [ PDF ]
  • Ruirui Huang, and G. Edward Suh, IVEC: Off-Chip Memory Integrity Protection for Both Security and Reliability, Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), June 2010. [ ACM ]
  • Ruirui Huang, Daniel Y. Deng, and G. Edward Suh, Orthrus: Efficient Software Integrity Protection on Multi-Cores, Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), March 2010. [ ACM ]

2009

  • Daniel Y. Deng, Andrew H. Chan, and G. Edward Suh, Hardware Authentication Leveraging Performance Limits in Detailed Simulations and Emulations, Proceedings of the 46th Design Automation Conference (DAC'09), July 2009. [ ACM ]
  • Keun Sup Shim, Myong Hyon Cho, Michel Kinsy, Tina Wen, G. Edward Suh, and Srinivas Devadas, Static Virtual Channel Allocation in Oblivious Routing, Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2009. [ ACM ]
  • Michel Kinsy, Myong Hyon Cho, Tina Wen, Edward Suh, Marten van Dijk, and Srinivas Devadas, Application-Aware Deadlock-Free Oblivious Routing, Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA), June 2009. [ ACM ]

2008

  • Myong Hyon Cho, Chih-Chi Cheng, Michel Kinsy, G. Edward Suh, and Srinivas Devadas, Diastolic Arrays: Throughput-Driven Reconfigurable Computing, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'08), November 10-23, 2008. [ IEEE ]
  • Srinivas Devadas, G. Edward Suh, Sid Paral, Richard Sowell, Thomas Ziola, and Vivek Khandelwal, Design and Implementation of PUF-Based “Unclonable” RFID ICs for Anti-Counterfeiting and Security Applications, Proceedings of the IEEE International Conference on RFID, April 16-17, 2008. [ IEEE ]

2007

  • G. Edward Suh, Charles W. O'Donnell, and Srinivas Devadas, AEGIS: A Single-Chip Secure Processor, IEEE Design & Test of Computers, vol.24, no.6, pp.570-580, Nov.-Dec. 2007. [ IEEE ]
  • Charles W. O'Donnell, G. Edward Suh, Marten van Dijk, and Srinivas Devadas, Memoization Attacks and Copy Protection in Partitioned Applications, Proceedings of the 2007 IEEE Workshop on Information Assurance, West Point, NY, June 2007. [ PDF ]
  • G. Edward Suh, and Srinivas Devadas, Physical Unclonable Functions for Device Authentication and Secret Key Generation, Proceedings of the 44th Design Automation Conference (DAC'07), San Diego, CA, June 2007. [ PDF ]

2006

  • Marten van Dijk, Dwaine Clarke, Blaise Gassend, G. Edward Suh, and Srinivas Devadas, Speeding up Exponentiation using an Untrusted Computational Resource , Designs, Codes and Cryptography, Volume 39, Number 2, Pages 253-273, May 2006. [ PDF ]

2005

  • Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, and Srinivas Devadas, Extracting Secret Keys from Integrated Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 10, Pages 1200-1205, October 2005. [ PDF ]
  • G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, and Srinivas Devadas, Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions, Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005. (This memo is a slightly updated version) [ PS ] [ PDF ] [ SLIDES(PPT) ]
  • Dwaine Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk and Srinivas Devadas, Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data, 2005. Proceedings of the 2005 IEEE Symposium on Security and Privacy (This memo is a slightly updated version) [ PS ] [ PDF ]

2004

  • G. Edward Suh, Jae W. Lee, David X. Zhang, and Srinivas Devadas, Secure Program Execution via Dynamic Information Flow Tracking, Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI), pages 85-96, Boston, MA, October 2004. [ PS ] [ PDF ] [ SLIDES ]
  • Jae W. Lee, Daihyun Lim, Blaise Gassend, G. Edward Suh, Marten van Dijk, and Srinivas Devadas, A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication Applications, Proceedings of the Symposium on VLSI Circuits, pages 176-179, Honolulu, HI, June 2004. [ PS ] [ PDF ]
  • G. Edward Suh, Larry Rudolph, and Srinivas Devadas, Dynamic Partitioning of Shared Cache Memory, The Journal of Supercomputing, 28(1), pages 7-26, April 2004. [ PDF ]

2003

  • G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, and Srinivas Devadas, Efficient Memory Integrity Verification and Encryption for Secure Processors, Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO36), pages 339-350, San Diego, CA, December 2003. [ PS ] [ PDF ] [ SLIDES ]
  • Dwaine Clarke, Srinivas Devadas, Marten van Dijk, Blaise Gassend, and G. Edward Suh, Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking, Proceedings of the 9th International Conference on the Theory and Application of Cryptology and Information Security (Asiacrypt 2003), Lecture Notes in Computer Science (LNCS), Vol. 2894, pages 188-207, Taipei, Taiwan, November 2003. [ PS ] [ PDF ]
  • G. Edward Suh, Blaise Gassend, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas, The AEGIS Processor Architecture for Tamper-Evident and Tamper-Resistant Processing, Proceedings of the 17th International Conference on Supercomputing (ICS'03), pages 160-171, San Francisco, CA, June 2003. (Revised version) [ PS ] [ PDF ] [ SLIDES ]
  • Prabhat Jain, G. Edward Suh, and Srinivas Devadas, Intelligent SRAM (ISRAM) for Improved Embedded System Performance, Proceedings of the 40th Design Automation Conference (DAC'03), pages 869-874, Anaheim, CA, June 2003. [ PS ] [ PDF ]
  • Blaise Gassend, G. Edward Suh, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas, Caches and Hash Trees for Efficient Memory Integrity Verification, Proceedings of the High Performance Computer Architecture 9 (HPCA9), pages 295-306, Anaheim, CA, February 2003. [ PS ] [ PDF ]

2002

  • G. Edward Suh, Srinivas Devadas, and Larry Rudolph, A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning, Proceedings of the High Performance Computer Architecture 8 (HPCA8), pages 117-118, Boston, MA, February 2002. [ PS ] [ PDF ] [ SLIDES ]

2001

  • G. Edward Suh, Larry Rudolph, and Srinivas Devadas, Effects of Memory Performance on Parallel Job Scheduling, Proceedings of the 7th International Workshop on Job Scheduling Strategies for for Parallel Processing (JSSPP 2001), Lecture Notes in Computer Science (LNCS), Vol. 2221, pages 116-132, Cambridge, MA, June 2001. [ PS ] [ PDF ]
  • G. Edward Suh, Larry Rudolph, and Srinivas Devadas, Dynamic Cache Partitioning for Simultaneous Multithreading Systems, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS'01), pages 635-641, Anaheim, CA, August 2001. (Best paper award) [ PS ] [ PDF ] [ SLIDES ]
  • G. Edward Suh, Srinivas Devadas, and Larry Rudolph, Analytical Cache Models with Application to Cache Partitioning, Proceedings of the 15th International Conference on Supercomputing (ICS'01), pages 1-12, Sorrento, Italy, June 2001. [ PS ] [ PDF ] [ SLIDES ]

Book Chapters

  • A. Sadeghi, D. Naccache (Eds.), Towards Hardware-Intrinsic Security, Springer, 2010. (ISBN: 978-3-642-14451-6)

MS Theses/PhD Dissertations

  • Taejoon Song, Prediction-Guided Performance-Energy Trade-off with Continuous Run-time Adaptation, MS Thesis, Cornell University, May 2016. [ PDF ]
  • Danny Y. Deng, Flexible and Efficient Accelerator Architecture for Runtime Monitoring, Doctoral Dissertation, Cornell University, May 2016. [ PDF ]
  • Wing-Kei (KK) Yu, Hybrid Memories for Energy Efficient Computing Systems, Doctoral Dissertation, Cornell University, January 2016.
  • Rui Xu, Information Flow Analysis for Security Verification of Hardware, MS Thesis, Cornell University, August 2015.
  • Daniel Lo, Hardware Architectures For Secure, Reliable, And Energy-Efficient Real-Time Systems, Doctoral Dissertation, Cornell University, August 2015. [ eCommons ]
  • Ruirui (Ray) Huang, Detecting And Mitigating Concurrency Bugs, Doctoral Dissertation, Cornell University, May 2013. [ eCommons ]
  • G. Edward Suh, AEGIS: A Single-Chip Secure Processor, MIT CSAIL CSG-TR-489 (Doctoral Dissertation), September 2005. [ PDF ]

Unrefereed Publications

ACM and IEEE-mandated Copyright Notice

The documents listed above are posted as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder.

 
pubs.txt · Last modified: 2017/02/10 05:30 by gs272