Hardware provides an important foundation for any software security mechanisms. In particular, hardware must be able to protect and isolate security-critical software components from less trusted parts. For example, in cloud computing, a high-security virtual machine (VM) must be isolated from low-security VMs. In safety-critical cyber-physical systems (CPS) such as self-driving cars, safety-critical components such as autonomous controllers must be securely isolated from the rest of a system such as passenger entertainment systems. Unfortunately, today’s computing systems cannot provide strong isolation or security assurance. This project aims to develop a verifiably secure computing system and apply it to build a secure autonomous driving vehicle. For this project, we are collaborating with Andrew Myers and Mark Campbell at Cornell.
There are three main thrusts in this project. In the first thrust, we are developing a multi-core processor where all software-visible information flows are tightly controlled. In particular, today’s processor designs are vulnerable to timing-channel attacks and we are developing protection mechanisms to enable complete timing isolation. This architecture will be able to provide comprehensive isolation among software components.
Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh, SecDCP: Secure Dynamic Cache Partitioning for Efficient Timing Channel Protection, To appear in Proceedings of the the 53rd Design Automation Conference (DAC), June 2016
Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh, Lattice Priority Scheduling: Low-Overhead Timing Channel Protection for a Shared Memory Controller, To appear in Proceedings of the 22nd International Symposium on High-Performance Computer Architecture (HPCA), February 2016.
Yao Wang, Andrew Ferraiuolo, and G. Edward Suh, Timing Channel Protection for Memory Controllers, Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014.
Yao Wang and G. Edward Suh, Efficient Timing Channel Protection for On-Chip Networks, Proceedings of the 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2012.
In the second thrust, we are developing tools and methodologies to enable formally verifying information flow properties of hardware designs. The goal is to be able to formally prove that our multi-core processor design is indeed secure.
Danfeng Zhang, Yao Wang, G. Edward Suh, and Andrew C. Myers, A Hardware Design Language for Timing-Sensitive Information-Flow Security, Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015. [ ACM-Authorize ]
Finally, we are working on developing a secure self-driving vehicle based on the new secure multi-core.