Prof. Zhiru Zhang and Prof. Ed Suh received a $500K research grant from the NSF/SRC STARSS program for their project, titled “Automatic Synthesis of Verifiably Secure Hardware Accelerators”. The project aims to develop ASSURE, a design automation framework that synthesizes verifiably secure hardware accelerators from high-level programming languages.

NSF Award Abstract

A new NSF/SRC grant on building secure accelerators