Mulong Luo (from UCSD) will join our research group as a new PhD student. He will initially work on the secure CPS project. Welcome!
Prof. Aaron Wagner, Prof. Ed Suh, and Prof. Negar Kiyavash (UIUC) received an NSF medium grant to study information leaks in computer and communication systems using new information theoretic techniques. The details can be found in the award abstract on
Prof. Suh’s paper, “A technique to build a secret key in integrated circuits for identification and authentication applications”, which was presented in 2004 Symposium on VLSI Circuits, has been selected as the most often cited among all papers presented in
Alex Rucker, an undergraduate who has been working in our research group, will be joining the PhD program at Stanford. He plans to study computer architecture so we may still see him often at conferences.
Judy Stephen’s M.Eng. poster on “Hardware Accelerator for Convolutional Neural Network” was selected as the best poster in the AI / Pattern Recognition (Computer Vision, Machine Learning, Robotics) category at the 2017 ECE MEng Poster Session. Congratulations!
Our paper, titled “Secure Information Flow Verification with Mutable Dependent Types“, is accepted for publication at this year’s Design Automation Conference (DAC). The paper is authored by Andrew Ferraiuolo, Weizhe Hua, Andrew Myers, and G. Edward Suh, and proposes a new
Our paper on verifying practical security architecture implementations using information flow, titled “Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis”, is accepted for publication at ASPLOS 2017.
Yao Wang successfully defended his thesis research “Efficient and Verifiable Timing Channel Protection for Multi-Core Processors”. He will be joining a start-up company, Waltz Networks, after graduation. Congratulations!
Weizhe (Will) Hua from USC will join our research group as a new PhD student. He will initially start working on the secure processor/accelerator project.
Prof. Zhiru Zhang and Prof. Ed Suh received a $500K research grant from the NSF/SRC STARSS program for their project, titled “Automatic Synthesis of Verifiably Secure Hardware Accelerators”. The project aims to develop ASSURE, a design automation framework that synthesizes